The Field Effect Transistor
The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals. One type of transistor is known as the field effect transistor (FET).
The terminals of a field effect transistor (FET) are commonly named source (S), gate (G) and drain (D). In the FET a small amount of voltage is applied to the gate (G) in order to control current flowing between the source (S) and the drain (D). In FETs the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal, enlarging or constricting the channel and thereby controlling the current flowing between the source and the drain.
FIG. 1 illustrates a FET 100 comprising a p-type substrate (or a p-well in the substrate), and two spaced-apart n-type diffusion areas—one of which will serve as the “source”, the other of which will serve as the “drain” of the transistor. The space between the two diffusion areas is the “channel”. A thin dielectric layer is disposed over the substrate in the neighborhood of the channel, and a “gate” structure is disposed over the dielectric layer atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.) Electrical connections (not shown) may be made to the source, the drain, and the gate. The substrate may be grounded, or it may be biased at a desired voltage depending on applications.
Generally, when there is no voltage on the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity) is applied to the gate, there is a “field effect” in the channel between the source and the drain, and current can flow between the source and the drain, and can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
FET 100 is exemplary of a MOSFET (metal oxide semiconductor FET) transistor. With the specified “n” and “p” types shown above, an “n-channel MOSFET” can be formed. With opposite polarities (swapping “p” for “n” in the diffusions, and “n” for “p” in the substrate or well), a p-channel FET can be formed. In CMOS (complementary metal oxide semiconductor), both n-channel and p-channel MOS transistors may be used, and are often paired with one another.
An integrated circuit (IC) device may comprise many millions of FETs on a single semiconductor “chip” (or “die”), measuring only a few centimeters on each side. Several IC chips may be formed simultaneously, on a single “wafer”, using conventional semiconductor fabrication processes including deposition, doping, photolithography, and etching. After all the chips are formed, they can be singulated from the wafer.
The Floating Gate Transistor
A floating gate transistor is generally a transistor structure, broadly based on the FET, as described hereinabove. As illustrated in FIG. 2, floating gate transistor 200 has a source and a drain, but rather than having only one gate, it has two gates which are called control gate (CG) and floating gate (FG). It is this arrangement of control gate and floating gate which enables the floating gate transistor to function as a memory cell, as described hereinbelow.
The floating gate is disposed over tunnel oxide (comparable to the gate oxide of the FET). The floating gate is a conductor, the tunnel oxide is an insulator (dielectric material). Another layer of oxide (interpoly oxide, also a dielectric material) separates the floating gate from the control gate.
Since the floating gate is a conductor, and is surrounded by dielectric material, it can store a charge. Electrons can move around freely within the conductive material of the floating gate (which comports with the basic definition of a “conductor”).
Since the floating gate can store a charge, it can exert a field effect on the channel region between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove. Mechanisms for storing charges on the floating gate structure, as well as removing charges from the floating gate, are described hereinbelow.
Generally, if a charge is stored on the floating gate, this represents a binary “1”. If no charge is stored on the floating gate, this represents a binary “0”. (These designations are arbitrary, and can be reversed so that the charged state represents binary “0” and the discharged state represents binary “1”.) That represents the programming “half” of how a floating gate memory cell operates. The other half is how to determine whether there is a charge stored on the floating gate—in other words, to “read” the memory cell. Generally, this is done by applying appropriate voltages to the source, drain and gate terminals, and determining how conductive the channel is. Some modes of operation for a floating gate memory cell are described hereinbelow.
Normally, the floating gate non-volatile memory (NVM) cell has only a single “charge-storing area”—namely, the conductive floating gate (FG) structure, and can therefore only store a single bit of information (binary “1” or binary “0”). More recently, using a technology referred to as “multi-level cell” (MLC), two or more bits can be stored in and read from the floating gate cell.
The NROM Memory Cell
Another type of memory cell, called a “nitride, read only memory” (NROM) cell, has a charge-storage structure which is different from that of the floating gate memory cell and which permits charges to be stored (or trapped) in two separate charge-storage areas. Generally, the two separate charge storage areas are located within a non-conductive layer disposed between the gate and the underlying substrate, such as a layer of nitride formed in an oxide-nitride-oxide (ONO) stack underneath the gate. The non-conductive layer acts as a charge-trapping medium. Generally, electrical charges will stay where they are put in the charge-trapping medium, rather than being free to move around as in the example of the conductive floating gate of the floating gate memory cell. A first bit of binary information (binary “1” or binary “0”) can be stored in a first portion (such as the left-hand side) of the charge-trapping medium, and a second bit of binary information (binary “1” or binary “0”) can be stored in a second portion (such as the right-hand side) of the charge-trapping medium. An alternative viewpoint is that different charge concentrations can be considered for each bit of storage. Using MLC technology, at least two bits can be stored in and read from each of the two portions (charge storage areas) of the charge-trapping medium (for a total of 4 bits), similarly 3 bits or more than 4 bits may be identified.
FIG. 3 illustrates a basic NROM memory cell 300, which may be viewed as an FET with an “ONO” structure inserted between the gate and the substrate. (One might say that the ONO structure is “substituted” for the gate oxide of the FET.)
The ONO structure is a stack (or “sandwich”) of bottom (lower) oxide 322, a charge-trapping material such as nitride 324, and a top (upper) oxide 326. The ONO structure may have an overall thickness of approximately 10-25 nm, such as 18 nm, as follows:                the bottom oxide layer 322 may be from 3 to 6 nm, for example 4 nm thick;        the middle nitride layer 324 may be from 3 to 8 nm, for example 4 nm thick; and        the top oxide layer 326 may be from 5 to 15 nm, for example 10 nm thick.        
The NROM memory cell has two spaced apart diffusions 314 and 316 (which can function as source and drain, as discussed hereinbelow), and a channel region 320 defined in the substrate 312 between the two diffusion regions 314 and 316, and a gate 328 disposed above the ONO stack 321.
In FIG. 3, the diffusions are labeled “N+”. This means that they are regions in the substrate that have been doped with an electron donor material, such as phosphorous or arsenic. These diffusions are typically created in a larger region which is a p-type cell well (CW) is doped with boron (or indium or both). This is the normal “polarity” for an NVM cell employing electron injection (but which may also employ hole injection, such as for erase). With opposite polarity (boron or indiun implants in an n-type cell well), the primary injection mechanism would be for holes, which is generally accepted to be not as effective as electron injection. One skilled in the art will recognize that the concepts disclosed herein can be applied to opposite polarity devices.
The charge-trapping material 324 is non-conductive, and therefore, although electrical charges can be stored in the charge-trapping material, they are not free to move around, and they will generally stay where they are stored. Nitride is a suitable charge-trapping material. Charge trapping materials other than nitride may also be suitable for use as the charge-trapping medium. One such material is silicon dioxide with buried polysilicon islands. A layer (324) of silicon dioxide with polysilicon islands would be sandwiched between the two layers of oxide (322) and (326). Alternatively, the charge-trapping layer 324 may be constructed by implanting an impurity, such as arsenic, into a layer of silicon dioxide deposited on top of the bottom oxide 322.
Memory cell 300 is generally capable of storing at least two bits of data—at least one bit(s) in a first storage area of the nitride layer 324 represented by the dashed circle 323, and at least one bit(s) in a second storage area of the nitride layer 324 represented by the dashed circle 325. Thus, the NROM memory cell can be considered to comprise two “half cells”, each half cell capable of storing at least one bit(s). It should be understood that a half cell is not a physically separate structure from another half cell in the same memory cell. The term “half cell”, as it may be used herein, is used herein only to refer to the “left” or “right” bit storage area of the ONO stack 321 (nitride layer 324). The storage areas 325, 323 may variously be referred to as “charge storage areas”, “charge trapping areas”, and the like, throughout this document. (The two charge storage areas may also be referred to as the right and left “bits”.)
Each of the storage areas 325, 323 in the charge-trapping material 324 can exert a field effect on the channel region 320 between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove (FIG. 2).
Generally, if a charge is stored in a given storage area of the charge-trapping material, this represents a binary “1”, and if no charge is stored in a given storage area of the charge-trapping material, this represents a binary “0”. (Again, these designations are arbitrary, and can be reversed so that the charged state represents binary “0” and the discharged state represents binary “1”.) That represents the programming “half” of how an NROM memory cell operates. The other half is how to determine whether there is a charge stored in a given storage area of the charge-trapping material—in other words, to “read” the memory cell. Generally, this is done by applying appropriate voltages to the diffusion regions (functioning as source and drain) and gate terminals, and determining how conductive the channel is.
Modes of Operation
Generally, the modes of operation for any NVM memory cell (either floating gate or NROM) include “program”, “erase” and “read”. Modes of operation for NROM are now discussed.
Program generally involves injecting electrons into the charge storage areas of the NROM or other NVM cell, typically by a process known as channel hot electron (CHE) injection. Exemplary voltages to program (by CHE injection of electrons) the right bit (right bit storage area) of an NROM cell may include:                the left BL (acting as source, Vs) is set to 0 volts        the right BL (acting as drain, Vd) is set to +5 volts        the gate (Vg) is set to +8-10 volts        the substrate (Vb) is set to 0 volts        
and the bit storage area above the drain (right BL) becomes programmed. To program the left bit storage area, source and drain are reversed—the left bitline serves as the drain, and the right bitline serves as the source.
Erase may involve injecting holes into the charge storage areas of the NROM cell, typically by a process known as hot hole injection (HHI). Generally, holes cancel out electrons (they are electrically opposite), on a one-to-one basis. Exemplary voltages to erase (by HHI injection of holes) the right bit of an NROM cell may include:                the left BL (acting as source, Vs) is set to float        the right BL (acting as drain, Vd) is set to +5 volts        the gate (Vg) is set to −7 volts        the substrate (Vb) is set to 0 volts        
and the bit storage area above the drain (right BL) becomes erased. To erase the left bit storage area, source and drain are reversed—the left bitline serves as the drain, and the right bitline serves as the source.
Read may involve applying voltages to the terminals of the memory cell and, based on subsequent current flow, ascertaining the threshold voltage of the charge storage area within the cell. Generally, to read the right bit of the NROM cell, using “reverse read”,                the right BL (acting as source, Vs) is set to 0 volts        the left BL (acting as drain, Vd) is set to +2 volts        the gate (Vg) is set to +5 volts        the substrate (Vb) is set to 0 volts        
and the bit storage area above the source (right BL) can be read. To read the left bit storage area, source and drain are reversed—the left bitline serves as the source, and the right bitline serves as the drain.
The following table summarizes the operating conditions discussed above, for an NROM cell, using representative (exemplary, approximate, illustrative, non-limiting) voltages.
ProgramEraseReadDrain Voltage+5 +5+2Source Voltage0float0Gate Voltage+10−7+5Substrate0 00Comment(s)the bit abovethe bit abovethe bit abovethe drain becomesthe drain becomesthe source is readprogrammederased
It is worth noting that during the read operation, the bias conditions are quite similar to those used during programming, except for lower voltage magnitudes, and this can result in the injection of electrons from the drain to the charge-trapping area above the drain (or, in the case of a floating gate cell, into the floating gate), thereby affecting the programming of the selected memory cell.
“Reading” an NROM Cell
Reading an NROM memory cell may involve applying voltages to the terminals of the memory cell comparable to those used to read a floating gate memory cell, but reading may be performed in a direction opposite to that of programming. Generally, rather than performing “symmetrical” programming and reading (as is the case with the floating gate memory cell, described hereinabove), the NROM memory cell is usually programmed and read “asymmetrically”, meaning that programming and reading occur in opposite directions. This is illustrated by the arrows in FIG. 3. Programming is performed in what is termed the forward direction, and reading is performed in what is termed the opposite or reverse direction. For example, generally, to program the right storage area 323 (in other words, to program the right “bit”), electrons flow from left (source) to right (drain). To read the right storage area 323 (in other words, to read the right “bit”), voltages are applied to cause electrons to flow from right to left, in the opposite or reverse direction. For example, generally, to program the left storage area 325 (in other words, to program the left “bit”), electrons flow from right (source) to left (drain). To read the left storage area 325 (in other words, to read the left “bit”), voltages are applied to cause electrons to flow from left to right, in the opposite or reverse direction. See, for example, U.S. Pat. No. 6,768,165.
“Read” is generally done by measuring the Vt of a cell (or half-cell), and associating the measured Vt with a program level (such as “0” or “1”). Although the Vts of the cells are measured on an individual basis, it is generally necessary to determine a distribution of Vts for many cells in order to associate the measured Vt of a given cell with a program level, with confidence. For example—if only one cell were to be read, and its threshold voltage were to be found to be at or very near the RV between two program levels, it may be difficult to say, with certainty, at which of two program levels the single cell was programmed, since its threshold voltage may have moved slightly upward or slightly downward since it was programmed. This is a benefit of reading bits one block at a time—to obtain a statistically meaningful sample of Vts across a number of cells.
Memory Array Architecture, Generally
Memory arrays are well known, and comprise a plurality (many, including many millions) of memory cells organized (including physically arranged) in rows (usually represented in drawings as going across the page, horizontally, from left-to-right) and columns (usually represented in drawings as going up and down the page, from top-to-bottom).
As discussed hereinabove, each memory cell comprises a first diffusion (functioning as source or drain), a second diffusion (functioning as drain or source) and a gate, each of which has a voltage applied thereto in order for the cell to be operated, as discussed hereinabove. (The substrate (or well) may also have a voltage applied thereto, such as 0 volts.)
Generally, the first diffusions (usually designated “source”) of a plurality of memory cells are connected to a first bit line, which may be designated “BL(n)”, and second diffusions (usually designated “drain”) of the plurality of memory cells are connected to a second bit line which may be designated “BL(n+1)”. Typically, the gates of a plurality of memory cells are connected to common word lines (WL).
The bitlines may be “buried bitline” diffusions in the substrate, and may serve as the source/drain diffusions for the memory cells. The wordlines may be polysilicon structures and may serve as the gate elements for the memory cells.
FIG. 4 illustrates an array of NROM memory cells (labeled “a” through “i”) connected to a number of word lines (WL) and bit lines (BL). For example, the memory cell “e” has its gate connected to WL(n), its source (left hand diffusion) is connected to BL(n), and its drain (right hand diffusion) is connected to BL(n+1). The nine memory cells illustrated in FIG. 4 are exemplary of many millions of memory cells that may be resident on a single chip.
Notice, for example that the gates of the memory cells “e” and “f” (to the right of “e”) are both connected to the same word line WL(n). (The gate of the memory cell “d” to the left of “e” is also connected to the same word line WL(n).) Notice also that the right hand terminal (diffusion) of memory cell “e” is connected to the same bit line BL(n+1) as the left-hand terminal (diffusion) of the neighboring memory cell “f”. In this example, the memory cells “e” and “f” have two of their three terminals connected together.
The situation of neighboring memory cells sharing the same connection—the gates of neighboring memory cells being connected to the same word line, the source (for example, right hand diffusion) of one cell being connected to the drain (for example left hand diffusion) of the neighboring cell—is even more dramatically evident in what is called “virtual ground architecture” wherein two neighboring cells actually share the same diffusion. In virtual ground array architectures, the drain of one memory cell may actually be the same diffusion which is acting as the source for its neighboring cell. Examples of virtual ground array architecture may be found in U.S. Pat. Nos. 5,650,959; 6,130,452; and 6,175,519, incorporated in their entirety by reference herein.
The bitlines (BLs) mentioned above may extend in parallel with one another, through the array (or a portion thereof). A single buried bitline (BB) may be a single diffusion shared by two adjacent cell transistors, and may be referred to herein as a diffusion bitline (DBL). The diffusion bitline (DBL) is a diffusion, functioning as a conductive line, which is physically disposed (“buried”) within the surface of the substrate.
A cell transistor may be formed by an ONO stack which is disposed on the surface of the substrate, generally between adjacent bitlines (BB, dbl). The ONO stack includes a layer of silicon nitride (nitride), which can trap (store) electrons and holes. A gate electrode, which may be doped (to be conductive) polysilicon, is disposed on the ONO stack, and may be a portion of an elongate wordline extending through the array (or a portion thereof).
An inter-level dielectric (ILD) may be disposed on the substrate to support patterns of metallization for interconnecting cell transistors. A portion of the pattern may comprise metal bitlines (MBLs). Contacts to the buried bitlines may be made by metal-filled plugs extending through the ILD to the buried bitlines, such as at intervals of every 16 cells. (It is generally not necessary to have one bitline contact per cell, and a contact area occupies area which otherwise could be used for cell transistors.)
In some of the memory array illustrations presented herein, the wordlines may extend horizontally through the array (or a portion thereof), and the bitlines may extend vertically through the array (or a portion thereof), intersecting the wordlines at right angles (90 degrees) thereto. Or, in some of the illustrations, the memory array may be rotated so that the wordlines extend vertically and the bitlines extend horizontally.
Generally, the cell transistors described herein may be “dual bit” transistors, such as NROM, having two bit storage (charge-trapping) areas, which may be referred to as the “left bit” and the “right bit”.
Drain-Side and Source-Side Sensing
Generally, for an NROM cell having two bit storage areas, one over the drain (D) and another over the source (S), reading the bit over the source (S) may be performed by setting the drain “read” voltage (Vdr) to approximately +2 volts, such as 1.4 volts, and setting the source voltage (Vs) to approximately 0 volts (or ground). For example, with reference to FIG. 3, to read the “right” bit 323, use the left diffusion 314 as drain (D) and the right diffusion 316 as source (S). To read the “left” bit 325, use the right diffusion 316 as drain (D) and the left diffusion 314 as source (S).
With Vdr on the drain (D), the program level (as represented by Vt) stored over the source (S) may be sensed. Generally, to sense the Vt, current is measured, such as the current flowing into the drain (D) or the current coming out of the source (S). However, since these two currents are not identical, one may choose to perform either “drain-side” sensing (sensing the current going into the drain) or “source-side” sensing (sensing the current coming out of the source). Either the drain (D) or the source (S) may be used as the “sensing node”.
Global Bitlines (GBLs) and Local Bitlines (LBLs)
The NVM memory cells discussed herein are “based on” FETs (compare FIGS. 1, 2 and 3), and comprise two spaced-apart diffusions which may function as source (S) and drain (D), and a gate (G), and a channel formed between the source (S) and the drain (D) based on a voltage stored or trapped in a medium (floating gate, or nitride layer) disposed above the channel. The gate (G) of a given memory cell may be a portion of a wordline (WL), and the two diffusions (S,D) of the memory cell may be a portion of two corresponding, neighboring bitlines, and may be referred to as diffusion bitlines (DBLs).
In order to gain access to the memory cells of a memory array, external circuitry (not shown) is provided to select given wordlines and bitlines, to read, program or erase the memory cells.
Generally, it is not practical to connect the external circuitry (such as select transistors) directly to the diffusion bitlines (DBLs), and various metal interconnect layers (“M#”) are involved to effect the desired connections. In the case of the bitlines, this may involve local bitlines (LBLs) and global bitlines (GBLs).
Generally, the local bitline (LBL) is a metal line which is strapped to (connected in parallel with) the diffusion bitline (DBL) to improve the conduction, since DBL resistance tends to be relatively high. For example, local bitlines (LBLs) may be formed in a first metal layer (“M1”). Generally, the capacitances of both the DBL and LBL are summed to provide a total bitline capacitance. Higher up in the interconnect layers, such as at a third metal layer (“M3”), global bitlines (GBLs) are provided, which are connected to the external circuitry (such as select transistors) for applying voltages to the bitlines (such as may be required for program, erase and read operations). Global bitlines (GBLs) may be connected to Local bitlines (LBLs) by select transistors.
The mere presence of conductive lines and elements can introduce “stray”, generally undesirable capacitances, referred to herein as “parasitic capacitances”. A reason that these parasitic capacitances are generally undesirable, in the context of reading memory cells, is that they can “steal” current, by providing a “leakage” path. So, for example, when trying to read a memory cell programmed to a given voltage, the measured voltage may appear sufficiently lower to result in a false (erroneous) reading. When current leaks, voltage drops, generally according to the well known Ohm's law where E (voltage)=I (current) times R (resistance). More current leaking means more voltage dropping.
A “classic” capacitor generally comprises two conductive electrodes separated by a dielectric. All else being equal, in a capacitor, capacitance increases with the size of the conductive electrode(s).
Generally, stray (“parasitic”) capacitances resulting from metal bitlines (MBLs) are much greater than those resulting from diffusion bitlines (DBLs), partially due to their size being bigger.
U.S. Pat. No. 7,042,778 (2006), incorporated by reference herein, discloses a flash array implementation with local and global bit lines. As noted therein, generally, semiconductor memories, including flash memory, are commonly built using multi-layering wiring having different “metal levels”. A semiconductor memory having local and global bit lines may be manufactured so that local bit lines are located on a different metal level than global bit lines. Select transistors may be used to connect selected ones of the local bitlines to selected ones of the global bitlines.
U.S. Pat. No. 6,665,221 (2003), incorporated by reference herein, discloses that memory devices may include blocks of memory cells arranged in columns with each column of memory cells coupled to a local bit line. Such memory devices further include global bit lines having multiple local bit lines selectively coupled to each global bit line, with each global bit line extending to local bit lines in each memory block of a memory sector.
Multi-level Programming
In early NVM memory cells, there were generally only two program levels (or states), which represented binary “0” and binary “1”, and this is referred to as “single level programming” (SLC). Generally, the program level is determined by the threshold voltage created by electrons (or holes) stored in the floating gate (of an FG cell) or in the charge-trapping medium (such as nitride layer, in NROM). For example, a binary “0” may have been represented by a threshold voltage (Vt) less than 4.0 volts, and a binary “1” may have been represented by a threshold voltage greater than 4.0 volts.
In modern NVM memory cells, four or more program levels are possible, representing, for example, binary “00” (zero), binary “01” (one), binary “10” (two) and binary “11” (three). This (having more than two program levels) is referred to as “multi-level programming” (MLC), and exemplary threshold voltages representing these four program levels might be, for example:                the center value for “11” equals approximately 4.0 volts        the center value for “01” equals approximately 4.4 volts        the center value for “00” equals approximately 4.8 volts        the center value for “10” equals approximately 5.4 volts        
Thus, it is evident that multi-level programming is much more “sensitive” than single level programming and, when reading the contents of a memory cell, small changes or differences in measured voltage can lead to erroneous results.
On the Use of Reference Cells
Non-volatile memory (NVM) cells may have data bits stored therein that may be read, such as by means of a sense amplifier (SA). When reading a memory cell, a current flowing into the drain or out of the source may be measured, in order to determine the Vt of the charge storage area above the source (or, in the case of a floating gate memory cell, the Vt of the floating gate), and a voltage may be ascertained, which corresponds to a program level.
Many NVM arrays employ a “reference cell” as the basis for comparing the output of an “array cell” for a read operation. Both of these cells—the reference cell and the array cell—are memory cells, such as flash cells, and may be substantially identical with one another, although they may be located in different portions of the overall memory array (and, of course, on the same integrated circuit (IC) chip). The use of a reference cell may help compensate for changes in the overall array, such as due to voltage variations and temperature, and ensure a fairly stable reference for read operations.
Reference cells are memory cells that are programmed to one or more predetermined levels related to reading the contents (program level, data bits stored in) of the array cells. See, for example, U.S. Pat. No. 7,123,532 (Saifun, 2006) and U.S. Pat. No. 6,954,393 (Saifun, 2005).
Using reference cells to determine the program level of an array cell being read is somewhat analogous to “color matching”. For example, when a dentist is trying to determine a patient's tooth color, for manufacturing a prosthetic (false tooth), he may hold a card with reference colors (generally, all slightly different shades of white) up against the patient's tooth, comparing the reference colors to the patient's tooth color, looking for the best match. When holding a color sample against the patient's tooth, the dentist may determine that the tooth is either lighter than or darker than the color sample.
In the context of reading using reference cells, usually a value for Vt obtained from an array cell being read is compared against a “known” value from a reference cell and, using the sense amplifier (SA), it is determined whether the value read from the array cell is greater than the value retrieved from the reference cell. It is generally very important that the paths leading from the sense amps to the array cells are “matched” with the paths to the reference cells, and that they are operated in the same manner (for example, using the same drain drivers and Vds to read reference cells as are used to read the array cells).
Read Disturb
As used herein, “flash cell” is synonymous with “memory cell”, and includes “array cells”, as distinguished from “reference cells”. Generally, array cells are programmed with data or code based on usage (a user storing data or code, and data changing during usage), and reference cells are programmed only once, by the manufacturer.
As mentioned above, an NROM cell has two charge storage (trapping) areas, and is therefore sometimes referred to as having two “bits”—a left bit and a right bit. See, for example, FIG. 3.
When reading the right bit 323, a positive voltage (approximately 2 volts, for sake of this discussion) is put on the left diffusion 314, serving as drain (D). The right diffusion 316 serves as source (S), and is set to approximately 0 volts. During read, the drain-to-source potential difference (Vds) is thus approximately 2 volts. When the left bit 325 is being read, the drain and source functions of the diffusions are reversed—the right diffusion 316 is used as drain (D) and the left diffusion 314 is used as source (S).
As mentioned above, the read operation is similar to the program operation, but using lower voltages. (During the read operation, Vds is approximately 2 volts. During the program operation, Vds is approximately 5 volts.) Given the nature (and physics) of the programming mechanism, a read operation can be considered to be a “soft program”.
The drain-to-source potential difference (Vds) which is used during read may be optimized for memory cell operation, and may be a value more like 1.4 volts than the exemplary 2 volts used herein.
Recall that during program, the bit above the drain is programmed, and the other bit above the source may be referred to as the “second bit”. And, during read, the bit above the source is read, and the other bit above the drain may be referred to as the “second bit”. Generally, if one bit is being operated upon (which may be referred to as the “bit of interest”), the other bit is referred to as the “second bit”, and may exert an influence on the operation. For example, when reading the right bit, the program level of the left bit may exert an influence on the result of the read operation, and this may be referred to as the “second bit effect”. So, any inadvertent (soft) programming of the second bit (left bit), such as when reading the bit of interest (right bit), can result in subsequent read errors when reading the bit of interest (right bit). For array bits, the disturb to the second bit itself is generally more important, because it is a bit by itself. The disturb through changing the second bit is a second order issue. The disturb on a reference cell is only through it's second bit because reference cells are typically used as 1 bit cells.
Read disturb is a phenomenon which may cause degradation of the logical state (Vt) of a flash memory cell (indifferent whether an array cell or a read cell) due to a read operation, and especially due to many (such as millions of) read operations. Generally, the larger the drain-to-source potential difference (Vds) and the larger the number of read operations, the greater the effect.
For reference cells, read disturb can be a very serious problem, since a given reference cell may need to be read many millions of times, many more times than a given array cell. In NVM designs, typically an NVM reference cell is used to define the logical state (program level) of the array cells. This reference cell may be used for reading a large amount of array cells.                For example, for an 8 Gbit (gigabit) 4 bit per cell NROM array with 256 sense amplifiers (SAs), each reference cell may serve 8388608 (8*1024*1024*1024/256/4) array NROM cells, each of which requires 2 read cycles.        Thus, in this example, the read disturb of the reference cell is enhanced by approximately 1.5e7 (15 million) times compared to an array cell with similar characteristics.        
In and of itself, the fact that reading one bit (such as the right bit) may partially program the other (“second”) bit (such as the left bit) would seem to not present a problem, if the left bit were not ever going to be used, or read, or if these bits do not affect the state of the other “interesting” bits. However, when reading an NROM cell, the Vt of the other (second) bit will exert an influence on the measurement of Vt for the bit being read, and this is called the “second bit effect”. When reading a two-bit cell, if the second bit is programmed or not, that will have an effect on the actual current that will be detected for the bit being read. When reading a cell which is completely “native” (not programmed), you may, for example, get a current such as 20 μA (microamps). However, when the second bit is programmed to the highest program level (highest Vt), the measured current may be much lower, for example, 15 μA instead of 20 μA.
The “second bit effect” (described in the previous paragraph) is different than “read disturb”, although they are related in that read disturb does affect the second bit. Factors other than read disturb, beyond the scope of this discussion, can also affect the second bit effect. As mentioned above, for array cells, the read disturb affects a real bit. Only for reference cells, does the read disturb affect the second bit only.
Commonly-owned patents disclose structure and operation of NROM and related ONO memory cells. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,768,192 and 6,011,725, 6,649,972 and 6,552,387.
Commonly-owned patents disclose architectural aspects of an NROM and related ONO array, (some of which have application to other types of NVM array), such as segmentation of the array to handle disruption in its operation, and symmetric architecture and non-symmetric architecture for specific products, as well as the use of NROM and other NVM array(s) related to a virtual ground array. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,963,465, 6,285,574 and 6,633,496.
Commonly-owned patents also disclose additional aspects at the architecture level, including peripheral circuits that may be used to control an NROM array, or the like. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,233,180, and 6,448,750.
Commonly-owned patents also disclose several methods of operation of NROM and similar arrays, such as algorithms related to programming, erasing, and/or reading such arrays. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,215,148, 6,292,394 and 6,477,084.
Commonly-owned patents also disclose manufacturing processes, such as the process of forming a thin nitride layer that traps hot electrons as they are injected into the nitride layer.
Some examples may be found in commonly-owned U.S. Pat. Nos. 5,966,603, 6,030,871, 6,133,095 and 6,583,007.
Commonly-owned patents also disclose algorithms and methods of operation for each segment or technological application, such as: fast programming methodologies in all flash memory segments, with particular focus on the data flash segment, smart programming algorithms in the code flash and EEPROM segments, and a single device containing a combination of data flash, code flash and/or EEPROM. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,954,393 and 6,967,896.
Where applicable, descriptions involving NROM are intended specifically to include related oxide-nitride technologies, including SONOS (Silicon-Oxide-Nitride-Oxide-Silicon), MNOS (Metal-Nitride-Oxide-Silicon), MONOS (Metal-Oxide-Nitride-Oxide-Silicon) and the like used for NVM devices. Further description of NVM and related technologies may be found at “Non Volatile Memory Technology”, Vol. 1 & 2 (2005), Vol. 3 (2006) and Vol. 4 (2007), published by Saifun Semiconductor; “Microchip Fabrication”, by Peter Van Zant, 5th Edition 2004; “Application-Specific Integrated Circuits” by Michael John Sebastian Smith, 1997; “Semiconductor and Electronic Devices”, by Adir Bar-Lev, 2nd Edition, 1999; “Digital Integrated Circuits” by Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, 2nd Edition, 2002 and materials presented at and through http://siliconnexus.com, “Design Considerations in Scaled SONOS Nonvolatile Memory Devices” found at: http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/presentations/bu_white_s onos_lehigh_univ.pdf, “SONOS Nonvolatile Semiconductor Memories for Space and Military Applications” found at: http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/papers/adams_d.pdf, “Philips Research—Technologies—Embedded Nonvolatile Memories” found at: http://www.research.philips.com/technologies/ics/nvmemories/index.html, and “Semiconductor Memory: Non-Volatile Memory (NVM)” found at: http://www.ece.nus.edu.sg/stfpage/elezhucx/myweb/NVM.pdf,
all of which are incorporated by reference herein in their entirety.
Glossary
Unless otherwise noted, or as may be evident from the context of their usage, any terms, abbreviations, acronyms or scientific symbols and notations used herein are to be given their ordinary meaning in the technical discipline to which the disclosure most nearly pertains. The following terms, abbreviations and acronyms may be used throughout the descriptions presented herein and should generally be given the following meaning unless contradicted or elaborated upon by other descriptions set forth herein. Some of the terms set forth below may be registered trademarks (®).
When glossary terms (such as abbreviations) are used in the description, no distinction should be made between the use of capital (uppercase) and lowercase letters. For example “ABC”, “abc” and “Abc”, or any other combination of upper and lower case letters with these 3 letters in the same order, should be considered to have the same meaning as one another, unless indicated or explicitly stated to be otherwise. The same commonality generally applies to glossary terms (such as abbreviations) which include subscripts, which may appear with or without subscripts, such as “Xyz” and “Xyz”. Additionally, plurals of glossary terms may or may not include an apostrophe before the final “s”—for example, ABCs or ABC's.                array memory cells may optionally be organized in an array of rows and columns, and may be connected to selected bit lines and word lines in the array. The array may be organized into various logical sections containing pluralities of memory cells, such as blocks, pages and sectors. Some of these sections may be physically isolated and operated independently from one another.        bit The word “bit” is a shortening of the words “binary digit.” A bit refers to a digit in the binary numeral system (base 2). A given bit is either a binary “1” or “0”. For example, the number 1001011 is 7 bits long. The unit is sometimes abbreviated to “b”. Terms for large quantities of bits can be formed using the standard range of prefixes, such as kilobit (Kbit), megabit (Mbit) and gigabit (Gbit). A typical unit of 8 bits is called a Byte, and the basic unit for 128 Bytes to 16K Bytes is treated as a “page”. That is the “mathematical” definition of “bit”. In some cases, the actual (physical) left and right charge storage areas of an NROM cell may be referred to as the left “bit” and the right “bit”, even though they may store more than one binary bit (with MLC, each storage area can store at least two binary bits). The intended meaning of “bit” (mathematical or physical) should be apparent from the context in which it is used.        BL short for bit line. The bit line is a conductor connected to the drain (or source) of a memory cell transistor.        byte A byte is commonly used as a unit of storage measurement in computers, regardless of the type of data being stored. It is also one of the basic integral data types in many programming languages. A byte is a contiguous sequence of a fixed number of binary bits. In recent years, the use of a byte to mean 8 bits is nearly ubiquitous. The unit is sometimes abbreviated to “B”. Terms for large quantities of Bytes can be formed using the standard range of prefixes, for example, kilobyte (KB), megabyte (MB) and gigabyte (GB).        CHE short for channel hot electron. CHE is an “injection mechanism” for injecting electrons into a charge storage area of an NVM memory cell.        CHEI short for channel hot electron injection. sometimes abbreviated “CHE”.        CMOS short for complementary metal oxide semiconductor. CMOS consists of n-channel and p-channel MOS transistors. Due to very low power consumption and dissipation, as well as minimization of the current in “off” state, CMOS is a very effective device configuration for implementation of digital functions. CMOS is a key device in state-of-the-art silicon microelectronics.                    CMOS Inverter: A pair of two complementary transistors (a p-channel and an n-channel) with the source of the n-channel transistor connected to the drain of the p-channel transistor and the gates connected to each other. The output (drain of the p-channel transistor) is high whenever the input (gate) is low and the other way round. The CMOS inverter is the basic building block of CMOS digital circuits.            NMOS: n-channel CMOS.            PMOS: p-channel CMOS.                        distribution overlap A number of cells programmed at a given program level may exhibit a distribution of threshold voltages. Usually, the distribution for one program level is separated from a distribution for another program level. However, due to threshold drift, one or both of the distributions may move towards the other, causing some of the threshold voltages to be the same. The region where the threshold voltages are the same for cells programmed at two different program levels is the distribution overlap.        disturb When applying a pulse to a specific bit by raising WL and/or BL voltages, neighboring bits located on the same WL and/or same BL might suffer from Vt shift that cause margin loss. The shift is called “disturb”. Disturbs are a fault type where the content of a cell is unintentionally altered when operating on another cell. These faults have similar characteristics to coupling faults, however, they have special neighborhood requirements.                    Disturb faults are generally caused by the presence of high/intermediate electric field stress on an insulating layer within the core memory cell. This electric field results in leakage current caused either by FN-tunneling, punchthrough, or channel hot electron injection. Whether a given mechanism is responsible for a particular disturb is a function of the operating conditions and the state of the investigated cell.            The IEEE Standard Definition and Characterization of Floating Gate Semiconductor Arrays disturb faults can be divided into the following:            Word-line erase disturb (WED): Exists when a cell under program (selected cell) causes another unprogrammed cell (unselected cell), sharing the same wordline, to be erased.            Word-line program disturb (WPD): Exists when a cell under program (selected cell) causes another unprogrammed cell (unselected cell), sharing the same wordline, to be programmed.            Bit-line erase disturb (BED): Exists when a cell under program (selected cell) causes another unprogrammed cell (unselected cell), sharing the same bit-line, to be erased.            Bit-line program disturb (BPD): Exists when a cell under program (selected cell) causes another unprogrammed cell (unselected cell), sharing the same bitline, to be programmed.            Read disturb (RD): During read operation, the bias conditions are the same as programming conditions (except for lower voltage magnitudes) and can result in the injection of elections from the drain to the charge storage medium, thus programming the selected cell or half cell. This is known as soft program. In addition, unselected erased cells may become programmed, and those that are programmed may become erased, giving rise to what is known as gate read erase and channel read program, respectively. Both of these disturbs that occurs on un-addressed cells are considered to be another form of read disturbs.                        EEPROM short for electrically erasable, programmable read only memory. EEPROMs have the advantage of being able to selectively erase any part of the chip without the need to erase the entire chip and without the need to remove the chip from the circuit. The minimum erase unit is 1 Byte and more typically a full Page. While an erase and rewrite of a location appears nearly instantaneous to the user, the write process is usually slightly slower than the read process; the chip can usually be read at full system speeds.        endurance Because they are written by forcing electrons through a layer of electrical insulation onto a floating gate (or charge-trapping medium), some NVM cells can withstand only a limited number of write and erase cycles before the insulation is permanently damaged, and the ability of the cell to function correctly is compromised. In modern Flash EEPROM, the endurance may exceed 1,000,000 write/erase cycles.        EPROM short for erasable, programmable read only memory. EPROM is a memory cell in which information (data) can be erased and replaced with new information (data).        erase a method to erase data on a large set of bits in the array, such as by applying a voltage scheme that inject holes or remove electrons in the bit set. This method causes all bits to reach a low Vt level. See program and read.        FC short for flash (memory) cell.        FET short for field effect transistor. The FET is a transistor that relies on an electric field to control the shape and hence the conductivity of a “channel” in a semiconductor material. FETs are sometimes used as voltage-controlled resistors. The terminals of FETs are called gate (G), drain (D) and source (S).        FG short for floating gate. The floating-gate transistor is a kind of transistor that is commonly used for non-volatile storage such as flash, EPROM and EEPROM memory. Floating-gate transistors are almost always floating-gate MOSFETs. Floating-gate MOSFETs are useful because of their ability to store an electrical charge for extended periods of time even without a connection to a power supply.        Flash memory Flash memory is a form of non-volatile memory (EEPROM) that can be electrically erased and reprogrammed. Flash memory architecture allows multiple memory locations to be erased or written in one programming operation. Two common types of flash memory are NOR and NAND flash. NOR and NAND flash get their names from the structure of the interconnections between memory cells. In NOR flash, cells are connected in parallel to the bit lines, allowing cells to be read and programmed individually. The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate. In NAND flash, cells are connected in series, resembling a NAND gate, and preventing cells from being read and programmed individually: the cells connected in series must be read in series.                    Some systems will use a combination of NOR and NAND memories, where a smaller NOR memory is used as software ROM and a larger NAND memory is partitioned with a file system for use as a random access storage area. NAND is best suited to flash devices requiring high capacity data storage. This type of flash architecture combines higher storage space with faster erase, write, and read capabilities over the execute in place advantage of the NOR architecture. See NAND, NOR.                        FN tunneling Field emission—also called Fowler-Nordheim tunneling—is the process whereby electrons tunnel through a barrier in the presence of a high electric field. This quantum mechanical tunneling process is an important mechanism for thin barriers, such as those in metal-semiconductor junctions on highly-doped semiconductors. Using FN tunneling, electrons can be moved to the floating gate of a MOSFET memory cell.        half cell “half cell” (or “half-cell”) is a term which is sometimes used to refer to the two distinct charge storage areas (left and right bits) of an NROM memory cell.        HHI short for hot hole injection. HHI is an “injection mechanism” for injecting holes into a charge storage area of an NVM memory cell. See CHE.        ILD short for inter-level (or inter-layer) dielectric. Generally, ILD is a relatively thick layer of oxide deposited on completed underlying structures (such as FETs), which will support a layer(s) of metal lines interconnecting the various underlying structures. Holes may be etched through the ILD and filled with metal to make contact with elements (such as source, drain, gate) of the underlying structures.        inhibit if it is desired to apply erase to a subset of bits, avoiding erase from other bits sharing the same bit lines (BLs), an inhibit signal may be applied on the others, for example, as a positive voltage on the gate, to avoid hole injection. This procedure is called inhibit.        MLC short for multi-level cell. In the context of a floating gate (FG) memory cell, MLC means that at least two bits of information can be stored in the memory cell. In the context of an NROM memory cell, MLC means that at least four bits of information can be stored in the memory cell—at least two bits in each of the two charge storage areas.        MOS short for metal oxide semiconductor.        MOSFET short for metal oxide semiconductor field-effect transistor. MOSFET is by far the most common field-effect transistor in both digital and analog circuits. The MOSFET is composed of a channel of n-type or p-type semiconductor material, and is accordingly called an NMOSFET or a PMOSFET. (The ‘metal’ in the name is an anachronism from early chips where gates were metal; modern chips use polysilicon gates, but are still called MOSFETs).        moving read reference as used herein, “moving read reference” refers to a technique, such as disclosed in U.S. Pat. No. 6,992,932, wherein reference voltages are determined to be used in reading cells programmed to a given program state. Generally, if an error is detected, such as by using error detection (ED) bits, the reference voltages may have to be adjusted until the error is resolved.        NAND NAND flash architecture memories are accessed much like block devices such as hard disks or memory cards. The pages are typically 512 or 2,048 or 4,096 bytes in size. Associated with each page are usually a few bytes (typically 12-16 bytes) that are used for storage of an error detection (ED) and correction checksum. The pages are typically arranged in blocks, such as 32 pages of 512 bytes, 64 pages of 2,048 bytes, or 64 pages of 4,096 bytes. With NAND architecture, programming may be performed on a page basis, but erasure can only be performed on a block basis.                    Most NAND devices are shipped from the factory with some bad blocks, which are typically identified and marked according to a specified bad block marking strategy. The first physical block (block 0) is always guaranteed to be readable and free from errors. Hence, all vital pointers for partitioning and bad block management for the device are located inside this block (typically a pointer to the bad block tables). If the device is used for booting a system, this block may contain the master boot record.                        nitride commonly used to refer to silicon nitride (chemical formula Si3N4). A dielectric material commonly used in integrated circuit manufacturing. Forms an excellent mask (barrier) against oxidation of silicon (Si). Nitride is commonly used as a hard mask or, in the case of an NVM memory cell having an ONO layer, as a charge-trapping material.        n-type semiconductor in which concentration of electrons is higher than the concentration of “holes”. See p-type.        NOR Reading from NOR flash is similar to reading from random-access memory, provided the address and data bus are mapped correctly. Because of this, most microprocessors can use NOR flash memory as execute in place (XIP) memory, meaning that programs stored in NOR flash can be executed directly without the need to copy them into RAM. NOR flash chips lack intrinsic bad block management, so when a flash block is worn out, the software or device driver controlling the device must handle this, or the device will cease to work reliably.        NROM short for nitride(d) read only memory. Generally, a FET-type device having a charge trapping medium such as a nitride layer for storing charges (electrons and holes) in two discrete areas, near the source and drain diffusions, respectively.        NVM short for non-volatile memory. NVM is computer memory that can retain the stored information even when not powered. Examples of non-volatile memory include read-only memory, flash memory, most types of magnetic computer storage devices (for example, hard disks, floppy disk drives, and magnetic tape), optical disc drives, and early computer storage methods, such as paper tape and punch cards. Non-volatile memory is typically used for the task of secondary storage, or long-term persistent storage. The most widely used form of primary storage today is a volatile form of random access memory (RAM), meaning that when the computer is shut down, anything contained in RAM is lost. Unfortunately most forms of non-volatile memory have limitations which make it unsuitable for use as primary storage. Typically non-volatile memory either costs more or performs worse than volatile random access memory. (By analogy, the simplest form of an NVM memory cell is a simple light switch. Indeed, such a switch can be set to one of two (binary) positions, and “memorize” that position.) NVM includes floating gate (FG) devices and NROM devices, as well a devices using optical, magnetic and phase change properties of materials.        ONO short for oxide-nitride-oxide. ONO is used as a charge storage insulator consisting of a sandwich of thermally insulating oxide, and charge-trapping nitride.        over-erase a condition that happens to some bits in a large bit set that are erased together, due to erase speed difference, due to the situation that some bits erase faster than other bits. Fast bits are particularly susceptible to over-erase. See erase.        oxide commonly used to refer to silicon dioxide (SiO2). Also known as silica. SiO2 is the most common insulator in semiconductor device technology, particularly in silicon MOS/CMOS where it is used as a gate dielectric (gate oxide); high quality films may be obtained by thermal oxidation of silicon. Thermal SiO2 forms a smooth, low-defect interface with Si, and can be also readily deposited by CVD.        poly short for polycrystalline silicon (Si). Heavily doped poly Si is commonly used as a gate contact in silicon MOS and CMOS devices.        p-type semiconductor in which concentration of “holes” is higher than the concentration of electrons. See n-type. Examples of p-type silicon include silicon doped (enhanced) with boron (B), Indium (In) and the like.        PAE short for program after erase. PAE is useful to avoid cells that experienced over-erase and significant Vt reduction, to become leaky and cause read errors to all cells sharing the same bitlines.        page Generally, a grouping of memory cells can be termed a word, a grouping of words can be termed a page, and a grouping of pages can be termed a sector. Data may be accessed for reading and programming (or writing) by word or by page, while an entire sector is commonly accessed for erasing.        PBE short for program before erase. PBE is useful to bring cells to a more-or-less uniform level prior to performing an erase operation. Particularly, if a cell has been erased a number of times, it may otherwise end up with a negative Vt, which is generally undesirable.        PFROM short program flashROM. an inner design block (of Saifun) that stores instructions that the inner embedded microcontroller performs on flash devices.        program a method to program a bit in an array, by applying a voltage scheme that injects electrons. This method causes an increase in the Vt of the bit that is being programmed. Alternatively, with “high Vt erase”, programming may be a lowering of the Vt of the memory cell. See erase and read. Program may sometimes, erroneously be referred to as “write”. See write.        program rate as used herein, “program rate” refers to the number of times that a memory cell (or half cell) is programmed to various program (or threshold voltage) levels, such as representing a binary “1” or “0”.        program time refers to the duration of a single program pulse, or the duration of the whole program sequence algorithm to program a bit set.        programmed “programmed” generally means that the threshold voltage (Vt) of a cell is above a predetermined “program verify” level (Vth).        PROM short for programmable read-only memory.        RAM short for random access memory. RAM refers to data storage formats and equipment that allow the stored data to be accessed in any order—that is, at random, not just in sequence. In contrast, other types of memory devices (such as magnetic tapes, disks, and drums) can access data on the storage medium only in a predetermined order due to constraints in their mechanical design.        read a method to read the digital data stored in the array. The read operation is usually performed in “blocks” of several cells. See erase and program.        refresh a part of the program or erase algorithms that checks the status of bits and applies pulses to bits that may have lost some of their Vt due to reliability margin loss.        retention Retention generally refers to the ability of a memory cell to retain charges inserted into the charge storage medium, such as a floating gate. The data retention of EPROM, EEPROM, and Flash may be limited by charge leaking from the floating gates of the memory cell transistors. Leakage is exacerbated at high temperatures or in high-radiation environments.        ROM short for read-only memory.        SA short for sense amplifier (or “sense amp”). A sense amplifier is generally used in conjunction with memory arrays to amplify a voltage coming off of a bit line. There are many versions of sense amplifiers used in memory chips.        sector a part of the array, usually larger than a page, which usually contains a few pages. A minimum erase might include a sector. For example:                    Erase Sector (ES): Group of cells that are erased by single erase command            Physical Sector (PS): Group of ES connected by single grid of Word Lines (WL) and Bit Lines (BL), sharing same set of drivers.                        SEI short for secondary electron injection (or simply “secondary injection”). SEI occurs as a result of impact ionization by CHE electrons (e1) near the drain diffusion, generating an electron-hole pair (e2-h2), the hole (h2) of which continues into the substrate whereat another impact ionization results in another electron-hole pair (e3-h3), and the e3 electron becomes injected into the charge storage area(s) of the memory cell.        Si Silicon, a semiconductor.        SI units The International System of Units (abbreviated SI from the French Le Système international d'unités) is the modern form of the metric system and is generally a system devised around the convenience of the number 10. It is the world's most widely used system of units, both in everyday commerce and in science. The SI system of units consists of a set of units together with a set of prefixes. There are seven “base units”, which are meter (abbreviated “m”, for length), kilogram (abbreviated “kg”, for mass), second (abbreviated “s”, for time), Ampere (abbreviated “A”, for electric current), Kelvin (abbreviated “K”, for thermodynamic temperature), mole (abbreviated “mol”, for the amount of a substance), and candela (abbreviated “cd”, for luminous intensity). A prefix may be added to the units to produce a multiple of the original unit. All multiples are integer powers of ten. For example, “kilo” denotes a multiple of a thousand and “milli” denotes a multiple of one-thousandth. Hence there are one thousand millimeters to the meter and one thousand meters to the kilometer.        SLC short for single level cell. In the context of a floating gate (FG) memory cell, SLC means that one bit of information can be stored in the memory cell. In the context of an NROM memory cell, SLC means that at least two bits of information can be stored in the memory cell.        slice a portion of a memory array, such as a group of bitlines, that are connected to one sense amplifier (sense amp, “SA”).        SONOS Si-Oxide-Nitride-Oxide-Si, another way to describe ONO with the Si underneath and the Poly gate on top.        SRAM short for static random access memory. SRAM is a type of semiconductor memory. The word “static” indicates that the memory retains its contents as long as power remains applied, unlike dynamic RAM (DRAM) that needs to be periodically refreshed (nevertheless, SRAM should not be confused with read-only memory and flash memory, since it is volatile memory and preserves data only while power is continuously applied). SRAM should not be confused with SDRAM, which stands for synchronous DRAM and is entirely different from SRAM, or with pseudostatic RAM (PSRAM), which is DRAM configured to function, to an extent, as SRAM.        substrate typically a wafer, of monocrystalline silicon. A substrate is often covered by an oxide layer (sometimes referred to as a “pad oxide layer”). Pad oxide is usually relatively thin, that is, in the range of about 50 to about 500 Angstroms (5-50 nm), and can be formed, for example, by thermal oxidation of the substrate. Pad oxide may also be prepared by other methods. For example, silicon dioxide or reactive precursors like silane could be deposited by chemical vapor deposition (CVD). A nitride layer (sometimes referred to as a “pad nitride layer”) may be formed to protect the pad oxide and the underlying substrate during various processing steps. It usually has a thickness in the range of about 100 Angstroms to about 6000 Angstroms (10-600 nm), such as in the range of about 1500 Angstroms to about 3000 Angstroms (150-300 nm). Conventional means can be used to apply the pad nitride, such as chemical vapor deposition (CVD).        TEHH short for Tunnel Enhanced Hot Hole injection. TEHH is an “injection mechanism”.        Units of Length Various units of length may be used herein, as follows:        
meterA meter is the SI unit of length, slightly longer than a yard.(m)1 meter = ~ 39 inches. 1 kilometer (km) = 1000meters = ~ 0.6 miles. 1,000,000 microns = 1 meter.1,000 millimeters (mm) = 1 meter. 100 centimeters(cm) = 1 meter.micronone millionth of a meter (0.000001 meter); also referred to(μm)as a micrometer.mil1/1000 or 0.001 of an inch; 1 mil = 25.4 microns.nanometerone billionth of a meter (0.000000001 meter).(nm)Angstromone tenth of a billionth of a meter. 10 Å = 1 nm.(Å)                verify a read operation after applying a program or erase pulse, that checks if the applied program or erase pulse moved the Vt to the target level (program-verify or erase-verify level).        virtual ground array a topological architecture of memory cells where there is an electrical connection between neighboring cells.        V short for voltage. Different voltages may be applied to different parts of a transistor or memory cell to control its operation, such as:        
Vbshort for bulk (or substrate) voltageVdshort for drain voltageVgshort for gate voltageVsshort for source voltageVtshort for threshold voltage                wafer In microelectronics, a wafer is a thin slice of semiconducting material, such as a silicon crystal, upon which microcircuits are constructed. There are multiple orientation planes in the silicon crystal that can be used. The planes are defined by the “Miller Indices” methodology. Common orientations classified by the “Miller indices” are (100), (011), (110), and (111).        wear leveling Wear levelling (also written wear leveling) refers to a technique for prolonging the service life of some kinds of erasable computer storage media, such as flash memory. EEPROM and flash memory media have individually erasable segments, each of which can be put through a finite number of erase cycles before becoming unreliable. This can be anywhere between 10,000 and 1,000,000 cycles, for example, for NAND flash devices. Wear-levelling attempts to work around these limitations by arranging data so that erasures and re-writes are distributed evenly across the medium. In this way, no single sector prematurely fails due to a high concentration of write cycles.        word line or wordline, (WL). A conductor normally connected to the gate of a memory cell transistor. The wordline may serve as the gate electrode of several memory cells.        write a combined method usually involving first erasing a large set of bits, then programming new data into the bit set; the erase step is not required but it is customary. See erase and program.        